4GB (x64/x72) DDR3 SDRAM                                            pdf: flyer

The W3J512M64G-XPBX and W3J512M72G-XPBX
are Microsemi’s latest family of high density/high
performance DDR3 SDRAM’s. These are designed to
support high performance processors, and chipsets.
The fi rst true x64/x72 UDIMM/SODIMM in a single
BGA package, including all terminations.
Product Features
DDR3 Data Rate = 800, 1066, 1333 Mb/s
VCC = VCCQ = 1.5V
Differential bidirectional data strobe byte
8-bit prefetch architecture
Eight internal banks for concurrent operation
Auto Refresh and Self Refresh Modes
On Die Termination (ODT), nominal and dynamic
for data, strobe and mask signals
Output driver calibration
Programmable CAS latency: 5, 6, 7, 8, 9 or 10
Posted CAS additive latency: 0, CL-1, CL-2
CAS# Write latency = 5, 6, 7 or 8 based on tCK
Fixed burst length of 8 (BL8) and burst chop of 4
(BC4) via the mode register
tCK range: 400 - 667MHz
Write leveling
Confi gured as 1-Rank x64 or x72-bit data
Lower voltage (1.35V) option available in same
package
* This product is under development, is not qualifi ed or characterized
and is subject to change or cancellation without notice.
Package
TBD x TBD mm, 375 Plastic Ball Grid Array
(PBGA), TBD mm2
5.5 mm package body thickness max
1.00 mm pitch, with larger balls for better second
level reliability
Benefi ts
TBD% space saving
47% I/O reduction
Footprint campatible with smaller densities
W3J128M64/72G and W3J256M64/72G
Reduced part count from 8/9 to 1
Reduced layer count
1.0mm pitch allows escape routing between balls
Designed for DDR3 fl y-by routing
Address / Command terminations included
Clock termination included
RZQ calibration resistors included
Suitable for hi-reliability applications
Commercial and industrial temperature ranges
Typically lower power at same